The present invention relates to the design of semiconductor integrated circuits, and more specifically to an analytical model for estimating delays of logic gates in a netlist before mapping the netlist to any particular technology library and prior to placing and routing the netlist.
Semiconductor integrated circuits are traditionally designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logical function. With standard cell technology, the schematic diagram or HDL specification is synthesized into standard cells of a specific cell library.
Each cell corresponds to a logical functions unit, which is implemented by one or more transistors that are optimized for the cell. The logic designer selects the cells according to the number of loads that are attached to the cell, as well as an estimated interconnection required for routing. The cells in the cell library are defined by cell library definitions. Each cell library definition includes cell layout definitions and cell characteristics. The cell layout definition includes a layout pattern of the transistors in the cell, geometry data for the cell""s transistors and cell routing data. The cell characteristics include a cell propagation delay and a model of the cell""s function. The propagation delay is a function of the internal delay and the output loading (or xe2x80x9cfan-outxe2x80x9d) of the cell.
A series of computer-aided design tools generate a netlist from the schematic diagram or HDL specification of the selected cells and the interconnections between the cells. The netlist is used by a floor planner or placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. The design tools then determine the output loading of each cell as a function of the number of loads attached to each cell, the placement of each cell and the routed interconnections.
A timing analysis tool is then used to identify timing violations within the circuit. The time it takes for a signal to travel along a particular path or xe2x80x9cnetxe2x80x9d from one sequential element to another depends on the number of cells in the path, the internal cell delay, the number of loads attached to the cells in the path, the length of the routed interconnections in the path and the drive strengths of the transistors in the path.
A timing violation may be caused by a number of factors. For example, a particular cell may not have a large enough drive strength to drive the number of loads that are attached to that cell. Also, exceptionally long routing paths may cause timing violations. Timing violations are eliminated by making adjustments at each stage in the layout process. For example, an under-driven cell may be fixed by changing the logic diagram to include a cell having a larger drive strength. Alternatively, the logic diagram can be changed to divide the loads between one or more redundant cells or buffer cells. An exceptionally long routing path can be corrected by adjusting the placement of the cells.
Once the timing violations have been corrected, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition, which can be used to fabricate the integrated circuit.
Few attempts have been made to estimate delay before a netlist has been mapped to a particular technology library and subsequently placed and routed. Unavailability of any wire length information as well as absence of exact load-delay behavior of generic (unmapped) logic elements makes delay estimation an open problem.
All estimations of wire lengths (and hence the wire loads) before placing the cells and routing their interconnections are significantly inaccurate and mislead the design tool using them. Mapping the netlist into specific cells of a particular technology library is therefore done without any delay information or with grossly inaccurate (statistical) delay information. Also, the transformation of large function blocks, such as multiple-input and multiple-output elements, into smaller logical functions or cells is also done with limited delay information. The technology mapping and transformations are subsequently improved upon iteratively with delay information obtained from placement and routing. As a result, the initial placement and routing is not timing driven since little or no timing information is available at this stage in the fabrication process.
In the past, delay models for unmapped netlists rely on an approximate calculation of the number of logic levels in each gate or cell. Thus, the gate delay estimation is based only on the type of gate. Other models have placed a restriction on the fan-out of each gate output to limit error in the gate delay estimation as the load increases. These two models are easy to use, but are not very accurate.
In another model, each gate model is described by estimated capacitances of its inputs, and delay (for a specific output pin of the gate) depends on the type of gate as well as the total capacitance of all input pins of other gates driven by this output pin. This model is quite accurate, but is not local enough. For example, delay along a particular path can depend on the input capacitances of gates that do not belong to the path if an output pin on that path drives input pins of gates that are not on the path.
Improved methods and analytical delay models are desired for estimating delays of cells in a netlist before mapping the netlist to a particular technology library and prior to placing and routing the netlist.
One aspect of the present invention relates to a pre-placement delay model for a logical function block of an integrated circuit design, which includes a fan-in count variable, a fan-out count variable and a delay variable. The fan-in count variable has a value indicative of a number of inputs to the logical function block. The fan-out count variable has a value indicative of the number of inputs of other logical function blocks that are driven by an output of the logical function block. The delay variable has a value that is a function of the binary logarithm of the fan-in count variable and the binary logarithm of the fan-out count variable.
Another aspect of the present invention relates to a method of modeling delay through a logical function block within an integrated circuit design prior to placement and routing. The method includes (a) identifying a fan-in count indicative of a number of inputs to the logical function block; (b) identifying a fan-out count indicative of a number of inputs to other logical function blocks in the integrated circuit design that are driven by an output of the logical function block; and (c) producing a propagation delay estimate for the logical function block as a function of the binary logarithm of the fan-in count and the binary logarithm of the fan-out count.
Yet another aspect of the present invention relates to a semiconductor cell library which, for each cell in the library, includes a functional model and a propagation delay model. The propagation delay model models propagation delay through the cell as a function of only two design variables, a fan-in count variable and a fan-out count variable. The fan-in count variable indicates a number of inputs to the cell, and the fan-out count variable indicates a number of inputs of other cells that are driven by an output of that cell.